A random test is performed for testing a processor. In the random test, a random instruction sequence including input data is produced based on a pseudo random number. A processor that is a device to be tested is caused to execute the produced instruction, thereby determining validity of an instruction execution result.
A method in which a test instruction is produced based on a random number has been proposed. In such test, an expected value produced by a simulation and a test instruction execution result of the device to be tested are compared to each other, and an advanced control function concerning a branching instruction is tested. In the test, a test instruction is produced, while an instruction for setting a condition code is produced as one of the randomly-produced test instructions. In the test instruction, a conditional branching instruction is added to the end of the condition code, and a branching failure instruction and a branching success instruction are added to the end of the conditional branching instruction. When the test instruction having the defined number of instructions is produced, the simulation is performed on one test instruction in the produced test instruction at a time. Then, the expected value is obtained by executing the test instruction sequence, and the expected value and the result value obtained by actually executing the test instruction are compared with each other to perform the test of the data processing device to be tested. When the expected value and the result value do not match each other, a signal indicating an error is outputted.
In the test, in order to exert a maximum capability of the advanced control function, a branching success instruction is operated after the subsequent branching failure instruction is operated in advance until a stage at which the condition code of the conditional branching instruction is set. For example, see Japanese patent Publication No. 6-56588.
In the test instruction, there are many condition code setting instructions whose results are expressed by the condition codes. In executing the test instruction, the condition code stored in a register is overwritten and changed every time the condition code setting instruction is executed. Accordingly, in cases where the result value at the end of the actual test instruction sequence and the expected value obtained by performing the simulation are compared to each other, it is impossible to recognize a setting error of the condition code in the middle of the test instruction sequence. When the result value and the expected value are compared at the end of the test instruction sequence, it is impossible to determine which condition code setting instruction in the test instruction sequence caused an error because the register is overwritten by the result of the instruction subsequent to the condition code setting. When the test is performed while a branching instruction comparing the results is added to the test instruction sequence every time the condition code setting instruction is executed such that the condition code is not overwritten, the advanced control function is interrupted by the branching instruction.